Architecture description
Introduction
Simple-CPU is a 32 bits RISC processor with linear memory access using load and store methods. It is based on as less as possible instructions with lots of parameters. This document will so describe natural cpu language with its encoding and then describe a user friendly assembly set of instructions that alias natural one.
Simple-CPU has 32 double word registers (32b width) named R00 to R31. twenty nine of them are for general use. R00 is resserved for program counter, R01 for stack pointer and R02 is used for flags and specific status or conf bits. R00 and R02 can be used in all instruction like general ones.
All instructions are 32 bits len even if they need less. All instructions need 1 cycle with instruction loading pipeline.
There is no distinction between program space and data space into memory. Instructions allways start on a 4 modulus address but data access can be done by byte, word or double word.
Instructions type
- Data acces instruction and Register loading
LOADi : load a byte, word, dword from memory,register or a direct value.
STORE : store a byte, word, dword into memory. - Register logic
AND : standard 32bits logic
OR : standard 32bits logic
XOR : standard 32bits logic
ROT : standard multiple type of bit shifting - Register arithmetics
ADDr : standard add/sub with options
ADDd : direct value add/sub
MUL : standard integer mutiplication storing result into two register
DIV : standard integer division - Conditionnal jump and bit manipulation
JB : jump if specified flag have specified value
CPYB : copy a specific bit into a specific destination bit
JMPd : unconditional jump
JMPr : unconditionnal jump to an address gives by a register
- Sub program jump
CALL : call of a sub function
RET : return from a subfunction
PUSH : push register on stack
POP : pop register on stack - My favorite
NOP : to do nothing
Internal architecture