Architecture description


Simple-CPU is a 32 bits RISC processor with linear memory access using load and store methods. It is based on as less as possible instructions with lots of parameters. This document will so describe natural cpu language with its encoding and then describe a user friendly assembly set of instructions that alias natural one.

Simple-CPU has 32 double word registers (32b width) named R00 to R31. twenty nine of them are for general use. R00 is resserved for program counter, R01 for stack pointer and R02 is used for flags and specific status or conf bits. R00 and R02 can be used in all instruction like general ones.

All instructions are 32 bits len even if they need less. All instructions need 1 cycle with instruction loading pipeline.

There is no distinction between program space and data space into memory. Instructions allways start on a 4 modulus address but data access can be done by byte, word or double word.

Instructions type

Internal architecture

Simple-Cpu The Simple CPU project The Simple CPU project
Un projet de disk91
Small CPU project