Synthese de l'avancement de la construction du processeur
Construction du coeur
Synthèse de l'avancement au travers de la couverture du jeu d'instruction :
| L'instruction est testée et validée |
| Les tests unitaires simples sont validés |
| L'instruction est implémentée |
| Instruction non couverte |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 |
21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Instruction |
Code instruction | Destination |
Opérande 1 | Opérande 2 |
| |
0 | 0 | Adresse absolue | JMP |
0 | 1 | Adresse absolue | CALL |
1 | 1 | 0 | | mode | v | bit | Rnn | Adresse relative | JB |
1 | 0 | 1 | | value | Rdd | Rnn | value | ADDd |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rdd | Rnn | Rmm | mode | | ADDr |
1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | Rdd | Rnn | Rmm | | AND |
1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rdd | Rnn | Rmm | | OR |
1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | Rdd | Rnn | Rmm | | XOR |
1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | Rdd | Rnn | step | dir | mode | | ROT |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | Rdd | Rnn | Rmm | mode | | MUL |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | Rdd | Rnn | Rmm | mode | type | | DIV |
1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | Rdd | valeur directe | mode | | LOADd |
1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | Rdd | | Rmm | mode | | LOADm |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | Rdd | Rnn | | mode | | LOADr |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | | NOP |
1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | | Rnn | Rmm | mode | | STORE |
1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | Rdd | Rnn | dest bit | mode | | src bit | CPYB |
1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | | Rnn | | | PUSH |
1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | Rdd | | | | POP |
1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | | Rnn | | | JMPr |
1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | | Rnn | | | CALLr |