Statut de la conception du processeur SC91-A

Processor advancement oberview

Instruction set implementation synthesis

This part lists the instructions and the status of each :

Instruction tested and validated
Unitary tests are performed and ok
Instruction synthesised
Instruction not yet built

31302928272625242322 21201918171615141312 11109876543210 Instruction
Code instructionDestination Opérande 1Opérande 2
00Adresse absolue JMP
01Adresse absolue CALL
110modevbitRnnAdresse relative JB
101valueRddRnnvalue ADDd
10000000RddRnnRmmmode ADDr
11110001RddRnnRmm AND
11110010RddRnnRmm OR
11110011RddRnnRmm XOR
11110100RddRnnstepdirmode ROT
11111000RddRnnRmmmode MUL
11111100Rddvaleur directemode LOADd
11111101RddRmmmode LOADm
11111110RddRnnmode LOADr
11111111 NOP
11101100RnnRmmmode STORE
11100000RddRnndest bitmodesrc bitCPYB
11100100Rnn PUSH
11100101Rdd POP
11101000Rnn JMPr
11101001Rnn CALLr

Simple-Cpu The Simple CPU project The Simple CPU project
Un projet de disk91
Small CPU project